/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __IM110GW_IT_H__ 
#define __IM110GW_IT_H__ 

#ifdef __cplusplus
 extern "C"{
#endif

/* Includes ------------------------------------------------------------------*/
#include "utils.h"
/** @addtogroup IM110GW_StdPeriph_Driver
  * @{
  */

typedef void (*PLIC_IRQHandlePtr)(void);
typedef enum{
    E_TIMER0_IRQ        = 1,
    E_TIMER1_IRQ        = 2,
    E_TIMER2_IRQ 		= 3,
    E_TIMER3_IRQ 		= 4,
    E_TIMER4_IRQ        = 5,
    E_TIMER5_IRQ        = 6,
    E_TIMER6_IRQ        = 7,
    E_TIMER7_IRQ        = 8,

    E_ASSI0_IRQ 		= 9, 
    E_ASSI1_IRQ 		= 10, 
    E_ASSI2_IRQ 		= 11, 
    E_ASSI3_IRQ 		= 12, 
    E_ASSI4_IRQ 		= 13, 
    E_ASSI5_IRQ 		= 14,

    //I2S
    E_I2S_IRQ 			= 15,
    //CAN
    E_IWDT_IRQ 			= 16,
    //WDT
    E_RTC_IRQ 			= 17,
    //RTC
    E_DMA0_IRQ   		= 18,
    //DMA
    E_EWM_IRQ 			= 19,
    // lpitimer_intr
    E_LPITIMER0_IRQ      = 20,
    E_LPITIMER1_IRQ      = 21,
    E_LPITIMER2_IRQ      = 22,
    E_LPITIMER3_IRQ      = 23,

    //RESERVE 23
    E_WAKEUP_IRQ        = 24,
    //QEI
    E_QEI0_IRQ_ERR_IRQ  = 25,

    //GPIO
    E_GPIOA_IRQ 		= 26,
    E_GPIOB_IRQ 		= 27,
    E_GPIOC_IRQ 		= 28,
    E_GPIOD_IRQ 		= 29,

    E_QEI_IRQ           = 31,
    E_LPI2C_IRQ         = 32,
    E_LPSPI_IRQ         = 33,
    E_EFLASH_IRQ        = 34,

    E_MPU_IRQ           = 38,
    E_ERM_IRQ           = 39,

    E_LPTIMER_CAN0_IRQ =40,
    E_LPTIMER_CAN1_IRQ =41,
    E_LPTIMER_CAN2_IRQ =42,

    E_CLK_FAULT_IRQ     =43,
    E_LUART_IRQ         =44,
    E_BOR_IRQ           =45,

    E_CAN0_IRQ          =46,   
    E_CAN1_IRQ          =47,   
    E_CAN2_IRQ          =48, 

    //RESERVE 49-50
    E_ASSI6_IRQ    = 49,
    E_ASSI7_IRQ    = 50,
    //MTU 51-88
    E_MTU_TGIA0_IRQ     = 51,
    E_MTU_TGIB0_IRQ     = 52,
    E_MTU_TGIC0_IRQ     = 53,
    E_MTU_TGID0_IRQ     = 54,
    E_MTU_TGIV0_IRQ     = 55,
    E_MTU_TGIE0_IRQ     = 56,
    E_MTU_TGIF0_IRQ     = 57,
    E_MTU_TGIA1_IRQ     = 58,
    E_MTU_TGIB1_IRQ     = 59,
    E_MTU_TGIV1_IRQ     = 60,
    E_MTU_TGIU1_IRQ     = 61,
    E_MTU_TGIA2_IRQ     = 62,
    E_MTU_TGIB2_IRQ     = 63,
    E_MTU_TGIV2_IRQ     = 64,
    E_MTU_TGIU2_IRQ     = 65,
    E_MTU_TGIA3_IRQ     = 66,
    E_MTU_TGIB3_IRQ     = 67,
    E_MTU_TGIC3_IRQ     = 68,
    E_MTU_TGID3_IRQ     = 69,
    E_MTU_TGIV3_IRQ     = 70,
    E_MTU_TGIA4_IRQ     = 71,
    E_MTU_TGIB4_IRQ     = 72,
    E_MTU_TGIC4_IRQ     = 73,
    E_MTU_TGID4_IRQ     = 74,
    E_MTU_TGIV4_IRQ     = 75,
    E_MTU_TGIU5_IRQ     = 76,
    E_MTU_TGIV5_IRQ     = 77,
    E_MTU_TGIW5_IRQ     = 78,
    E_MTU_TGIA6_IRQ     = 79,
    E_MTU_TGIB6_IRQ     = 80,
    E_MTU_TGIC6_IRQ     = 81,
    E_MTU_TGID6_IRQ     = 82,
    E_MTU_TGIV6_IRQ     = 83,
    E_MTU_TGIA7_IRQ     = 84,
    E_MTU_TGIB7_IRQ     = 85,
    E_MTU_TGIC7_IRQ     = 86,
    E_MTU_TGID7_IRQ     = 87,
    E_MTU_TGIV7_IRQ     = 88,
    //RESERVE 89-95
    E_PDB0_IRQ          = 89,
    E_PDB1_IRQ          = 90,
    E_RESERVE_91_IRQ    = 91,
    E_RESERVE_92_IRQ    = 92,
    E_RESERVE_93_IRQ    = 93,
    E_RESERVE_94_IRQ    = 94,
    E_RESERVE_95_IRQ    = 95,

    E_ADC01_SAMPLE_CONFLICT_IRQ  = 96,
    E_ADC23_SAMPLE_CONFLICT_IRQ  = 97,
    E_ADC01_ARBITRATION_IRQ    = 98,
    E_ADC23_ARBITRATION_IRQ    = 99,
    //XIO_IRQ 100-107
    E_IRQ0_IIN_IRQ      = 100,
    E_IRQ1_IIN_IRQ      = 101,
    E_LPTIMER_IRQ       = 102,
    //RESERVE 103
    E_RESERVE_103_IRQ   = 103,
    E_HSM_IRQ           = 104,

    E_INTC_CMPI01_IRQ   = 105,
    E_INTC_ADC0_IRQ     = 106,
    
    //ADC
    E_ADC01_TS_IRQ      = 107,
    E_ADC01_TS_IRQH     = 108,
    E_ADC01_TS_IRQL     = 109,
    E_ADC23_TS_IRQ      = 110,
    E_ADC23_TS_IRQH     = 111,
    E_ADC23_TS_IRQL     = 112,

    //POE
    E_POEN_OEI1_IRQ     = 113,
    E_POEN_OEI2_IRQ     = 114,
    E_POEN_OEI3_IRQ     = 115,

    E_CMP_IRQ           = 116,
    E_CMU_IRQ           = 117,
    E_PLLLOSS_IRQ       = 118,
} PLIC_IRQ;

typedef enum
{
    E_PLIC_PRIORITY_0   = 0,
    E_PLIC_PRIORITY_1   = 1,
    E_PLIC_PRIORITY_2   = 2,
    E_PLIC_PRIORITY_3   = 3,
    E_PLIC_PRIORITY_4   = 4,
    E_PLIC_PRIORITY_5   = 5,
    E_PLIC_PRIORITY_6   = 6,
    E_PLIC_PRIORITY_7   = 7,
} PLIC_Priority;

void PLIC_Init(PLIC_Priority threshold);
void PLIC_IRQInit(PLIC_IRQ irq, PLIC_Priority priority, PLIC_IRQHandlePtr handler);




#ifdef __cplusplus
}
#endif

#endif	/* __IM110GW_IT_H__ */
